1. Field of the Invention
The present invention relates to a semiconductor device including a semiconductor memory section with its input port and output port separated from each other.
2. Description of the Background Art
There have hitherto been proposed a variety of techniques regarding a multi-port memory with its input port and output port separated from each other. For example, Japanese Patent Application Laid-Open No. 09-54142 (1997) discloses a technique of arranging a bypass means of outputting data, having been inputted into an input port, directly to an output port to perform a test on a semiconductor memory device by use of the bypass means.
Further, other techniques regarding a semiconductor memory device are described in Japanese Patent Application Laid-Open Nos. 2001-23400 and 05-74198 (1993).
As in the technique described in Japanese Patent Application Laid-Open No. 09-54142 (1997), when the bypass function of outputting data, having been inputted into the input port, directly to the output port is to be realized in the semiconductor memory device, it is necessary to make a layout system as little complex as possible for size reduction of the device or simplification of the device production process.
While Japanese Patent Application Laid-Open No. 09-54142 (1997) describes a technique of arranging the input port and the output port to be close to each other in a layout, it does not describe a specific layout for arranging the bypass means. It is therefore not possible to obtain an optimum layout system from the technique of Japanese Patent Application Laid-Open No. 09-54142 (1997).